The present invention relates to switching packets of fixed length at a high speed.
A variety of such packet switching systems are known. Recently, there has been increased interest in obtaining high speed through the use of simplified protocol. A major function of such a high-speed packet switching system is to switch the packets in accordance with their header information and among the plurality of input ports and plurality of output ports by packet-multiplexing at a high speed, for example, about 150 Mbps. An excellent aspect of such high-speed packet switching systems is that the switching is accomplished by means of hardware. Such a system is exemplified by Japanese Patent Laid-Open No. 59-135994 and U.S. Pat. No. 4,516,238.
Japanese Patent Laid-Open No. 59-135994 multiplexes packets from a plurality of input ports into a common packet buffer. The addresses that are written as a part of the packet information are transferred to the output ports to which the same packets are to be outputted. At the output port sides, the transferred addresses are stored in first-in/first-out buffers, from which buffers the addresses are sequentially read out and used to read out the packets to be outputted from the common packet buffer and then subjected to parallel to series conversions until they are outputted. In U.S. Pat. No. 4,516,238 two-input/two-output switches are basically used and arranged in multiple stages to realize the packet switching function. THe two-input/two-output basic switches use a portion or all the bits of the address information of a packet header to switch the packets in a self-controlled manner. The system is composed of a cascade connection of three networks, that is, a classification network, a trap networks and extension network. Each of these three kinds of network is realized by a multi-stage connection of the aforementioned two-input/two-output basic switches.